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high voltage latch - up proof, dual spst switches data sheet ADG5421 / adg5423 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibili ty is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any pa tent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2013 analog d evices, inc. all rights reserved. technical support www.analog.com features latch - up immune under all circumstances h uman body model (h bm ) esd rating : 8 kv low on resistance : 13.5 9 v to 22 v dual - supply operation 9 v to 4 0 v single - supply operation 48 v supply maximum ratings fu lly specified at 15 v, 20 v, + 12 v, and + 36 v v dd to v ss analog signal range applications high voltage signal routing automatic test equipment analog front - end circuits precision d ata acquisition industrial i nstrumentation a mplifier gain select relay replacement functional block dia grams figure 1. ADG5421 figure 2. adg5423 general description the adg54 2 1 / adg5423 are monolithic indust rial , complementary metal oxide semiconductor (cmos) analog switch es containing two ind ependent latch - up immune single - pole/ sing le - throw (sp s t) switch es . each switch conducts equally well in bo th directions when on, and has an input signal range that extends to the power supplies. in the off condition, signal levels up to the supplies are bl ocked. both ADG5421 switches are turned on with a logic 1 input, whereas the adg5423 has one switch turned on and one switch turned off for a logic 1 input. the adg5423 exhibits break - before - make action for use in multiplexer applications. the ultralow on resistance and on - resi stance flatness of these switches make them ideal solutions for data acquisition and gain switching applications where low distortion is critical. the latch - up immune construction and high esd rating make these switches more robust in harsh environments. product highlights 1. trenc h isolation guards against latch - up. a dielectric trench separates the p channel and n channel transistors , thereby preventing latch - up even under severe overvoltage conditions. 2. low r on of 13.5 ? . 3. dual - supply operation. for applic ations where the analog signal is bipolar, the ADG5421 / adg5423 can operate from dual supplies up to 22 v. 4. single - supply o peration. for applications where the analog signal is unipolar, the ADG5421 / adg5423 can operate from a single - rail power supply up to 4 0 v. 5. 3 v logic compatible digital inputs: v i n h = 2.0 v, v i n l = 0.8 v. 6. no v l logic power supply required. 7. available in 10 - lead msop package. ADG5421 in1 in2 d2 s2 s1 d1 switches shown for a logic 0 input 11369-001 in1 s1 d1 adg5423 in2 d2 s2 switches shown for a logic 0 input 11369-002
ADG5421/adg5423 data sheet rev. 0 | page 2 of 20 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagrams ............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specificatio ns ..................................................................................... 3 15 v dual supply ....................................................................... 3 20 v dual supply ....................................................................... 4 12 v single supply ........................................................................ 5 36 v single supply ........................................................................ 6 continuous current per channel, sx or dx ..............................7 absolute maximum ratings ............................................................8 esd caution ...................................................................................8 pin configurations and function descriptions ............................9 typical performance characteristics ........................................... 10 test circuits ..................................................................................... 13 terminology .................................................................................... 15 applications information .............................................................. 16 trench isolation .......................................................................... 16 outline dimensions ....................................................................... 17 ordering guide .......................................................................... 17 revision history 9/ 13 revision 0 : initial versi on
data sheet ADG5421/adg5423 rev. 0 | page 3 of 20 specifications 15 v dual supply v dd = + 15 v 10%, v ss = ?15 v 10%, gnd = 0 v, unless otherwise noted. table 1 . parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range v dd to v ss v on resistance, r on 13.5 ? typ v s = 10 v, i s = ?10 ma; see figure 24 15 19 23 ? max v dd = +13.5 v, v ss = ?13.5 v on - resistance match between channels, ?r on 0.1 ? typ v s = 10 v, i s = ?10 ma 0.8 1.3 1.4 ? max on - resistance flatness, r flat (on) 1.8 ? typ v s = 10 v, i s = ?10 ma 2.2 2.7 3.1 ? max leakage currents v dd = +16.5 v, v ss = ?16.5 v source off leakage, i s (off) 0.05 na typ v s = 10 v, v d = ? 10 v; see figure 23 0.25 1 10 na max drain off leakage, i d (off) 0.05 na typ v s = 10 v, v d = ? 10 v; see figure 23 0.25 1 10 na max channel on leakage, i d (on), i s (on) 0.1 na typ v s = v d = 10 v; see figure 22 0.4 4 20 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.002 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 6 pf typ dynamic characteristics 1 t on 185 ns typ r l = 300 ?, c l = 35 pf 220 273 313 ns max v s = 10 v; see figure 29 t off 163 ns typ r l = 300 ?, c l = 35 pf 196 219 242 ns max v s = 10 v; see figure 29 break - before - make time delay, t d ( adg5423 only) 73 ns typ r l = 300 ?, c l = 35 pf 21 ns min v s1 = v s2 = 10 v; see figure 31 charge injection, q inj 95 pc typ v s = 0 v, r s = 0 ?, c l = 1 nf; see figure 30 off isolation ? 55 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz; see figure 25 channel - to - channel crosstalk ? 85 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; see figure 28 total harmonic distortion + noise 0.01 % typ r l = 1 k?, 15 v p - p, f = 20 hz to khz; see figure 26 ?3 db bandwidth 250 mhz typ r l = 50 ?, c l = 5 pf; see figure 27 insertion loss ?1 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz; see figure 27 c s (off) 12 pf typ v s = 0 v, f = 1 mhz c d (off) 13 pf typ v s = 0 v, f = 1 mhz c d (on), c s (on) 44 pf typ v s = 0 v, f = 1 mhz power requirements v dd = +16.5 v, v ss = ?16.5 v i dd 45 a typ digital inputs = 0 v or v dd 55 70 a max i ss 0.001 a typ digital inputs = 0 v or v dd 1 a max v dd /v ss 9/22 v min/v max gnd = 0 v 1 guaranteed by design; not subject to production test.
data shee t ADG5421/adg5423 rev. 0 | page 4 of 20 20 v dual supply v dd = + 20 v 10%, v ss = ?20 v 10%, gnd = 0 v, unless otherwise noted. table 2 . parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range v dd to v ss v on resistance, r on 12.5 ? typ v s = 15 v, i s = ?10 ma; see figure 24 14 18 22 ? max v dd = +18 v, v ss = ?18 v on - resistance match between channels, ? r on 0.1 ? typ v s = 15 v, i s = ?10 ma 0.8 1.3 1.4 ? max on - resistance flatness, r flat (on) 2.3 ? typ v s = 15 v, i s = ?10 ma 2.7 3.3 3.7 ? max leakage currents v dd = + 22 v, v ss = ? 22 v source off leakage, i s (off) 0.05 na typ v s = 15 v, v d = ? 1 5 v; see figure 23 0.25 1 10 na max drain off leakage, i d (off) 0.05 na typ v s = 1 5 v, v d = ? 15 v; see figure 23 0.25 1 10 na max channel on leakage, i d (on), i s (on) 0.1 na typ v s = v d = 1 5 v; see figure 22 0.4 4 20 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.002 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 6 pf typ dynamic characteristics 1 t on 168 ns typ r l = 300 ?, c l = 35 pf , v s = 10 v; see figure 29 199 243 276 ns max v s = 10 v; see figure 29 t off 156 ns typ r l = 300 ?, c l = 35 pf 184 204 218 ns max v s = 10 v; see figure 29 break - before - make time delay, t d ( adg5423 only) 65 ns typ r l = 300 ?, c l = 35 pf 38 ns min v s1 = v s2 = 10 v; see figure 31 charge injection, q inj 120 pc typ v s = 0 v, r s = 0 ?, c l = 1 nf; see figure 30 off isolation ? 55 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz; see figure 25 channel - to - channel crosstalk ? 85 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; see figure 28 total harmonic distortion + noise 0.01 % typ r l = 1 k?, 20 v p - p, f = 20 hz to 20 khz; see figure 26 ?3 db bandwidth 250 mhz typ r l = 50 ?, c l = 5 pf; see figure 27 insertion loss ?0.8 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz; see figure 27 c s (off) 11 pf typ v s = 0 v, f = 1 mhz c d (off) 12 pf typ v s = 0 v, f = 1 mhz c d (on), c s (on) 44 pf typ v s = 0 v, f = 1 mhz power requirements v dd = +22 v, v ss = ?22 v i dd 50 a typ digital inputs = 0 v or v dd 70 110 a max i ss 0.001 a typ digital inputs = 0 v or v dd 1 a max v dd /v ss 9/22 v min/v max gnd = 0 v 1 guaranteed by design; not subject to production test.
data sheet ADG5421/adg5423 rev. 0 | page 5 of 20 12 v single supply v dd = 12 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted. table 3 . parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance, r on 26 ? typ v s = 0 v to 10 v, i s = ?10 ma; see figure 24 30 38 44 ? max v dd = 10.8 v, v ss = 0 v on - resistance match between channels, ? r on 0.1 ? typ v s = 0 v to 10 v, i s = ?10 ma 1 1.5 1.6 ? max on - resistance flatness, r flat (on) 5.5 ? typ v s = 0 v to 10 v, i s = ?10 ma 6.8 8.3 12.3 ? max leakage currents v dd = +1 3 . 2 v, v ss = 0 v source off leakage, i s (off) 0.05 na typ v s = 1 v to 10 v, v d = 10 v to 1 v ; see figure 23 0.25 1 10 na max drain off leakage, i d (off) 0.05 na typ v s = 1 v to 10 v, v d = 10 v to 1 v ; see figure 23 0.25 1 10 na max channel on leakage, i d (on), i s (on) 0.1 na typ v s = v d = 1 v to 10 v; see figure 22 0.4 4 20 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.002 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 6 pf typ dynamic characteristics 1 t on 295 ns typ r l = 300 ? , c l = 35 pf 370 470 540 ns max v s = 8 v; see figure 29 t off 192 ns typ r l = 300 ? , c l = 35 pf 235 273 295 ns max v s = 8 v; see figure 29 break - before - make time delay, t d ( adg5423 only) 142 ns typ r l = 300 ? , c l = 35 pf 78 ns min v s1 = v s2 = 8 v; see figure 31 charge injection, q inj 55 pc typ v s = 6 v, r s = 0 ? , c l = 1 nf; see figure 30 off isolation ? 55 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz; see figure 25 channel - to - channel crosstalk ? 85 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; see figure 28 total harmonic distortion + noise 0.03 % typ r l = 1 k?, 6 v p - p, f = 20 hz to 20 khz; see figure 26 ?3 db bandwidth 290 mhz typ r l = 50 ? , c l = 5 pf; see figure 27 insertion loss ? 1.7 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz; see figure 27 c s (off) 14 pf typ v s = 6 v, f = 1 mhz c d (off) 15 pf typ v s = 6 v, f = 1 mhz c d (on), c s (on) 38 pf typ v s = 6 v, f = 1 mhz power requirements v dd = 13.2 v i dd 40 a typ digital inputs = 0 v or v dd 50 65 a max v dd 9/40 v min/v max gnd = 0 v, v ss = 0 v 1 guaranteed by design; not subject to production test.
data shee t ADG5421/adg5423 rev. 0 | page 6 of 20 36 v single supply v dd = 36 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted. table 4 . parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance, r on 14.5 ? typ v s = 0 v to 30 v, i s = ?10 ma; see figure 24 16 20 24 ? max v dd = 32.4 v, v ss = 0 v on - resistance match between channels, ? r on 0.1 ? typ v s = 0 v to 30 v, i s = ?10 ma 0.8 1.3 1.4 ? max on - resistance flatness, r flat (on) 3.5 ? typ v s = 0 v to 30 v, i s = ?10 ma 4.3 5.5 6.5 ? max leakage currents v dd = 39.6 v, v ss = 0 v source off leakage, i s (off) 0.05 na typ v s = 1 v to 3 0 v, v d = 3 0 v to 1 v; see figure 23 0.25 1 10 na max drain off leakage, i d (off) 0.05 na typ v s = 1 v to 30 v, v d = 3 0 v to 1 v ; see figure 23 0.25 1 10 na max channel on leakage, i d (on), i s (on) 0.1 na typ v s = v d = 1 v to 3 0 v; see figure 22 0.4 4 20 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.002 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 6 pf typ dynamic characteristics 1 t on 181 ns typ r l = 300 ? , c l = 35 pf 210 245 280 ns max v s = 18 v; see figure 29 t off 170 ns typ r l = 300 ? , c l = 35 pf 192 205 220 ns max v s = 18 v; see figure 29 break - before - make time delay, t d ( adg5423 only) 66 ns typ r l = 300 ? , c l = 35 pf 37 ns min v s1 = v s2 = 18 v; see figure 31 charge injection, q inj 110 pc typ v s = 18 v, r s = 0 ? , c l = 1 nf; see figure 30 off isolation ? 55 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz; see figure 25 channel - to - channel crosstalk ? 85 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; see figure 28 total harmonic distortion + noise 0.01 % typ r l = 1 k?, 18 v p - p, f = 20 hz to 20 khz; see figure 26 ?3 db bandwidth 260 mhz typ r l = 50 ? , c l = 5 pf; see figure 27 insertion loss ? 0.9 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz; see figure 27 c s (off) 13 pf typ v s = 18 v, f = 1 mhz c d (off) 16 pf typ v s = 18 v, f = 1 mhz c d (on), c s (on) 38 pf typ v s = 18 v, f = 1 mhz power requirements v dd = 39.6 v i dd 80 a typ digital inputs = 0 v or v dd 100 130 a max v dd 9/40 v min/v max gnd = 0 v, v ss = 0 v 1 guaranteed by design; not subject to production test.
data sheet ADG5421/adg5423 rev. 0 | page 7 of 20 continuous current p er channel, s x or d x table 5 . parameter 25c 85c 125c unit test conditions/comments continuous current, sx or dx msop ( ja = 133.1c/w ) v dd = +15 v, v ss = ?15 v 84 58 39 ma maximum v dd = +20 v, v ss = ?20 v 89 60 41 ma maximum v dd = 12 v, v ss = 0 v 67 47 32 ma maximum v dd = 36 v, v ss = 0 v 87 59 40 ma maximum
ADG5421/adg5423 data sheet rev. 0 | page 8 of 20 absolute maximum rat ings t a = 25c, unless otherwise noted. table 6 . parameter rating v dd to v ss 48 v v dd to gnd ?0.3 v to +48 v v ss to gnd +0.3 v to ?48 v analog inputs 1 v ss ? 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first digital inputs 1 v ss ? 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first peak current, sx or dx pins 300 ma (pulsed at 1 ms, 10% duty cycle maximum) continuous current, s x or d x 2 data + 15% temperature range operating ?40c to +125c storage ?65c to +150c junction temperature 150c thermal impedance , ja 10 - lead m sop (4 - layer board) 133.1c/w reflow soldering peak temperature, pb free as per jedec j - std -020 human body model (hbm) esd 8 kv 1 overvoltages at the inx, sx, and dx pins are clamped by internal diodes. limit current to the maximum ratings given. 2 see table 5 . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating can be applied at any one time. esd caution
data sheet ADG5421/adg5423 rev. 0 | page 9 of 20 pin configuration an d function descripti ons figure 3 . pin configuration table 7 . pin function descriptions pin no. nemonic description 1 s1 source terminal 1 . this pin can be an input or output. 2 s2 source terminal 2 . this pin can be an input or output. 3 nc no connect. not internally connected . 4 gnd ground (0 v) reference. 5 v dd most positive power supply potential. 6 in2 logic control input. 7 in1 logic control input. 8 v ss most negative power supply potential. 9 d2 drain terminal 2 . this pin can be an input or output. 10 d1 drain terminal 1 . this pin can be an input or output. table 8 . ADG5421 truth table in switch condition s 0 off 1 on table 9 . adg5423 truth table in switch 1 condition switch 2 condition 0 off on 1 on off notes 1. nc = no connec t . not internal l y connected. s1 1 s2 2 nc 3 gnd 4 v dd 5 d1 10 d2 9 v ss 8 in1 7 in2 6 11369-003 t o p view (not to scale) ADG5421/ adg5423
ADG5421/adg5423 data sheet rev. 0 | page 10 of 20 typical performance characteristics figure 4 . on resistance as a function of v s , v d (dual supply: 10 v, 15 v) figure 5. on resistance as a function of v s , v d (dual supply: 20 v) figure 6. on resistance as a function of v s , v d (single supply: 10 v, 12 v) figure 7. on resistance as a function of v s , v d (single supply: 36 v) figure 8 . on resistance as a function of v s (v d ) for different temperatures, 15 v dual supply figure 9 . on resistance as a function of v s (v d ) for different temperatures, 20 v dual supply 0 5 10 15 20 25 ?18 ?14 ?10 ?6 ?2 2 6 10 14 18 on resis t ance () v s , v d (v) t a = 25c v dd = +9v v ss = ?9v v dd = +10v v ss = ?10v v dd = +11v v ss = ?11v v dd = +13.5v v ss = ?13.5v v dd = +15v v ss = ?15v v dd = +16.5v v ss = ?16.5v 1 1369-004 0 2 4 6 8 10 12 14 16 ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 25 on resis t ance () v s , v d (v) t a = 25c v dd = +22v v ss = ?22v v dd = +20v v ss = ?20v v dd = +18v v ss = ?18v 1 1369-005 0 5 10 15 20 25 30 35 0 2 4 6 8 10 12 14 on resis t ance () v s , v d (v) t a = 25c v dd = 9v v ss = 0v v dd = 10v v ss = 0v v dd = 10.8v v ss = 0v v dd = 1 1v v ss = 0v v dd = 12v v ss = 0v v dd = 13.2v v ss = 0v 1 1369-006 0 2 4 6 8 10 12 14 16 0 5 10 15 20 25 30 35 40 45 on resis t ance () v s , v d (v) t a = 25c v dd = 39.6v v ss = 0v v dd = 36v v ss = 0v v dd = 32.4v v ss = 0v 1 1369-007 0 5 10 15 20 25 ?15 ?10 ?5 0 5 10 15 on resis t ance () v s , v d (v) v dd = +15v v ss = ?15v t a = +125c t a = +85c t a = +25c t a = ?40c 1 1369-008 0 5 10 15 20 25 ?20 ?15 ?10 ?5 0 5 10 15 20 on resis t ance () t a = +125c t a = +85c t a = +25c t a = ?40c v s , v d (v) v dd = +20v v ss = ?20v 1 1369-009
data sheet ADG5421/adg5423 rev. 0 | page 11 of 20 figure 10. on resistance as a function of v s (v d ) for different temperatures, 12 v single supply figure 11. on resistance as a function of v s (v d ) for different temperatures, 36 v single supply figure 12. leakage currents as a function of temperature, 15 v dual supply figure 13. leakage currents as a function of temperature, 20 v dual supply figure 14. leakage currents as a function of temperature, 12 v single supply figure 15. leakage currents as a function of temperature, 36 v single supply 0 5 10 15 20 25 30 35 40 024681012 v s , v d (v) on resistance ( ? ) t a = +125c t a = +85c t a = +25c t a = ?40c v dd = 12v v ss = 0v 11369-010 0 5 10 15 20 25 0 5 10 15 20 25 30 35 40 on resistance ( ? ) t a = +125c t a = +85c t a = +25c t a = ?40c v s , v d (v) v dd = 36v v ss = 0v 11369-011 02 55 07 51 0 01 2 5 leakage current (na) temperature (c) 0.6 0.4 ?0.2 0 ?0.4 0.2 v dd = +15v v ss = ?15v v bias = +10v/?10v i d , i s (on) + + i d , i s (on) ? ? i s (off) + ? i d (off) ? + i d (off) + ? i s (off) ? + 11369-012 0 25 50 75 100 125 leakage current (na) temperature (c) 0.4 0.2 ?0.2 0 ?0.4 ?0.6 v dd = +20v v ss = ?20v v bias = +15v/?15v i d , i s (on) + + i s (off) + ? i d (off) + ? i s (off) ? + i d , i s (on) ? ? i d (off) ? + 11369-013 0 255075100125 leakage current (na) temperature (c) 0.4 0.3 ?0.2 0 ?0.1 0.2 0.1 v dd = 12v v ss = 0v v bias = 1v/10v i d , i s (on) + + i d , i s (on) ? ? i s (off) + ? i d (off) ? + i d (off) + ? i s (off) ? + 11369-014 leakage current (na) temperature (c) 0 255075100125 0.4 0.2 ?0.2 0 ?0.4 ?0.6 v dd = 36v v ss = 0v v bias = 1v/30v i d , i s (on) + + i s (off) + ? i d (off) + ? i s (off) ? + i d , i s (on) ? ? i d (off) ? + 11369-015
ADG5421/adg5423 data sheet rev. 0 | page 12 of 20 figure 16 . off isolation vs. frequency figure 17 . crosstalk vs. frequency figure 18 . charge injection vs. source voltage (v s ) figure 19 . thd + n vs. frequency figure 20 . bandwidth figure 21 . t transition times vs. temperature 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 1k 10k 100k 1m 10m 100m 1g off isolation (db) frequency (hz) 11369-016 t a = 25c v dd = +15v v ss = ?15v ?120 ?100 ?80 ?60 ?40 ?20 0 10k 100k 1m 10m 100m 1g cross t alk (db) frequenc y (hz) 11369-017 t a = 25c v dd = +15v v ss = ?15v 0 50 100 150 200 250 300 ?20 ?10 0 10 20 30 40 charge injection (pc) v s (v) v dd = 15v, v ss = ?15v v dd = 20v, v ss = ?20v v dd = 12v, v ss = 0v v dd = 36v, v ss = 0v 1 1369-018 t a = 25c 0 0.01 0.02 0.03 0.04 0.05 0 5 10 15 20 thd + n (%) frequenc y (khz) v dd = 12 v , v ss = 0v , v s = 6v p-p v dd = 36 v , v ss = 0v , v s = 18v p-p v dd = 15 v , v ss = ?15 v , v s = 15v p-p v dd = 20 v , v ss = ?20 v , v s = 20v p-p 11369-019 0 ?0.5 ?1.0 ?1.5 ?2.0 ?2.5 ?3.0 ?3.5 ?4.0 ?4.5 ?5.0 1k 10k 100k 1m 10m 100m 1g insertion loss (db) frequency (hz) 11369-020 t a = 25c v dd = +15v v ss = ?15v 0 50 100 150 200 250 300 350 400 ?40 ?20 0 20 40 60 80 100 120 time (ns) temper a ture (c) v dd = 12 v , v ss = 0v v dd = 36 v , v ss = 0v v dd = 15 v , v ss = ?15v v dd = 20 v , v ss = ?20v 11369-021
data sheet ADG5421/adg5423 rev. 0 | page 13 of 20 test circuits figure 22. on leakage figure 23. off leakage figure 24. on resistance figure 25. off isolation figure 26. thd + noise figure 27. bandwidth sx nc nc = no connect dx 11369-022 a v d i d (on) sx dx v s a a v d i s (off) i d (off) 11369-023 i ds sx r on = v i ds dx v s v 11369-024 v out 50 ? network analyzer r l 50 ? inx v in sx dx 50 ? off isolation = 20 log v out v s v s v dd v ss 0.1f v dd 0.1f v ss gnd 11369-025 v out r s audio precision r l 1k ? inx v in sx dx v s v p-p v dd v ss 0.1f v dd 0.1f v ss gnd 11369-026 v out 50 ? network analyzer r l 50 ? inx v in sx dx insertion loss = 20 log v out with switch v out without switch v s v dd v ss 0.1f v dd 0.1f v ss gnd 11369-027
ADG5421/adg5423 data sheet rev. 0 | page 14 of 20 figure 28. channel-to-channel crosstalk figure 29. switching times, t on and t off figure 30. charge injection figure 31. break-before-make time delay channel-to-channel crosstalk = 20 log v out gnd s1 dx s2 v out network analyzer r l 50 ? r 50 ? v s v s v dd v ss 0.1f v dd 0.1f v ss 08487-028 v s inx sx dx gnd r l 300 ? c l 35pf v out v dd v ss 0.1f v dd 0.1f v ss ADG5421 adg5423 v in v in v out t on t off 50% 50% 90% 90% 50% 50% 011369-029 inx v out ADG5421 adg5423 v in v in v out off ? v out on q inj = c l ? v out sx dx v dd v ss v dd v ss v s r s gnd c l 1nf 11369-030 v s2 in1, in2 s2 d2 v s1 s1 d1 gnd r l 300 ? c l 35pf v out2 v out1 v dd v ss 0.1f v dd 0.1f v ss v in v out1 v out2 adg5423 t d t d 50% 50% 80% 80% 80% 80% 0v 0v 0v r l 300 ? c l 35pf 11369-031
data sheet ADG5421/adg5423 rev. 0 | page 15 of 20 terminology i dd i dd represents the positive supply current. i ss i ss represents the negative supply current. v d , v s v d and v s represent the analog voltage on terminal d and terminal s, respectively. r on r on is the o hmic resistance between terminal d and terminal s. ? r on ? r on represents t he d ifference between the r on of any two channels . r flat (on) r flat (on) represents the difference between the maximum and minimum value of on resistance as measured over the specified analog signal range . i s (off) i s (off) is the source leakage current with the switch off. i d (off) i d (off) is the drain leakage current wit h the switch off. i d (on), i s (on) i d (on) and i s (on) represent the channel leakage currents with the switch on. v inl v inl is the maximum input voltage for logic 0. v inh v inh is the minimum input voltage for logic 1. i inl , i inh i inl and i inh repres ent the low and high input currents of the digital inputs. c d (off) c d (off) represents the off switch drain capacitance, which is measured with reference to ground. c s (off) c s (off) represents the off switch source capacitance, which is measured with reference to ground. c d (on), c s (on) c d (on) and c s (on) represent on switch capacitances, which are measured with reference to ground. c in c in represents digital input capacitance. t on t on represents the d elay time between the 50% and 90% points of the digital input and switch on condition. t off t off represents the d elay time between the 50% and 90% points of the digital input and switch off condition. t d t d represents the o ff time measured between the 8 0% point of both sw itches when switching from one address state to another. off isolation off isolation is a measure of unwanted signal coupling through an off channel. charge injection charge injection is a measure of the glitch impulse transferred from the digital input to the analog output during switching. crosstalk crosstalk is a measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. bandwidth bandwidth is t he frequency at which the outpu t is attenuated by 3 db from its dc level . t otal h armonic d istortion + n oise (thd + n) the ratio of the harmonic amplitude plus noise of the signal to the fundamental is represented by thd + n .
ADG5421/adg5423 data sheet rev. 0 | page 16 of 20 applications informa tion the adg54xx family of switches and multiplexers provide a robust solution for instrumentation, industrial, aero space , and other harsh environments that are prone to la tch - up, which is an undesirable high current state that can lead to device failure and persists until the power supply is turned off. the ADG5421 / adg5423 high voltage switches allow single - supply operation from 9 v to 40 v and dual - supply operation from 9 v to 22 v. the ADG5421 / adg5423 (as well as other select devices within this family) achieve an 8 kv human body model esd rating, which provide s a robust solution , eliminating the need for separate protection circu itry designs in some applications . trench isolation in the ADG5421 / adg5423 , an insulating oxide layer (trench) is placed b etween the nmos and the pmos transistors of each cmos switch. parasitic junctions, which occur between the transistors in junction - isolated switches, are eliminated, and the result is a completely latch - up immune switch. in junction isolation, the n and p wells of the pmos and nmos transistors form a diode that is reverse - biased under normal operation. however, during overvoltage conditions, this diode can become forward - biased. t he t wo transistors form a silicon - controlled rectifier (scr) type circuit, causing a significant amplification of the current that , in turn, leads to latch - up. with trench isolation, this diode is removed, and the result is a latch - up immune switch. figure 32 . trench isolation 11369-032 nmos pmos p- w e l l n - w e l l buried oxide layer handle wafer t r e n c h
data sheet ADG5421/adg5423 rev. 0 | page 17 of 20 outline dimensions figure 33 . 10 - lead mini small outline package [msop] (rm - 10 ) dimensions shown in millimeters ordering guide model 1 temperature range package description package option branding ADG5421brmz ?40c to +125c 10 - lead mini small outline package [msop] rm -10 s47 ADG5421brmz -rl7 ?40c to +125c 10 - lead mini small outline package [msop] rm -10 s47 adg5423brmz ?40c to +125c 10 - lead mini small outline package [msop] rm -10 s3d adg5423brmz -rl7 ?40c to +125c 10 - lead mini small outline package [msop] rm -10 s3d 1 z = rohs compliant part. c o m p l i a n t t o j e d e c s t a n d a r d s m o - 1 8 7 - b a 0 9 1 7 0 9 - a 6 0 0 . 7 0 0 . 5 5 0 . 4 0 5 1 0 1 6 0 . 5 0 b s c 0 . 3 0 0 . 1 5 1 . 1 0 m a x 3 . 1 0 3 . 0 0 2 . 9 0 c o p l a n a r i t y 0 . 1 0 0 . 2 3 0 . 1 3 3 . 1 0 3 . 0 0 2 . 9 0 5.15 4.90 4.6 5 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05
ADG5421/adg5423 data sheet rev. 0 | page 18 of 20 notes
data sheet ADG5421/adg5423 rev. 0 | page 19 of 20 notes
ADG5421/adg5423 data sheet rev. 0 | page 20 of 20 notes ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d11369 - 0 - 9/13(0)

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